The generation of timing signals with fine resolution time delays finds important application in Automated Test Equipment (ATE) that is used for testing integrated circuit devices, where precise timing edge placement is required. A typical test requires that data from a Device Under Test (DUT) must be compared with expected data at a precisely controlled time and for a precisely controlled period. For example a tester might expect a signal on a data pin of the DUT to be low 2.435 ns after receipt of a trigger signal for a time period of 500 ps.
Typically ATE's use a timing vernier (essentially a delay generator) to generate these fine timing resolution signals from a precisely generated fixed frequency global clock signal. The timing vernier is essentially a delay generator capable of generating very small phase shifts, usually in the order of picoseconds of the global clock signal. Timing verniers are useful because the available timing resolution is determined by the difference between two precisely controlled propagation delay values, it is not constrained by minimum gate propagation delay.
Commercially available timing vernier devices are typically programmable via an eight bit code and can be retriggered at frequencies in the order of several hundred MHZ. The minimum resolution timing step of the vernier is determined by its minimum delay range divided by 255 (for an 8-bit code). However any number of bits (e.g. 16) may be used to subdivide the delay range. The delay range of the vernier is usually externally adjustable within its minimum delay range. The delay range of the vernier is usually externally adjustable within its minimum delay range and maximum delay range (dynamic range), by a current reference signal or a bias voltage signal.
Generally several timing verniers are used to divide the period of the global clock signal into several time slots. In typical ATE's the fixed frequency global clock signal is sent to all timing verniers from which all signal generation and sampling are measured. A disadvantage of a fixed frequency system is that the time slots are fixed relative to the period of the global clock signal.
Modern ATE's are required to test a wide variety of devices and thus there is a need for testers to operate over a wider frequency range in older to test this variety of devices.
Previous ATEs approached the problem of variable tester clock frequencies by computing the difference or remainder in delay between edges of the fixed global clock signal and the variable test clock signal and to compensate for this difference by using calibrated verniers. When the sum of the remainders is greater than one clock cycle, an additional clock cycle is inserted into the variable test clock signal. This requires complex control logic and is difficult to operate reliably.
A further problem is that because multiple timing verniers are used to generate tester clock frequencies process variations and temperature variations cause the vernier delays to drift and limits their resolution. This problem is particularly exacerbated by varying the frequency of the global clock signal.
Accordingly there is need for a timing vernier that may be locked to a variable frequency clock and that is minimally susceptible to process and operating condition variations.
Furthermore there is a need for a method for synchronizing multiple verniers to accommodate a variable frequency clock and to also reduce susceptibility to fluctuations in supply voltages.